Register Overview - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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By redirecting the signals as shown in

frame sync outputs are routed directly back to their respective inputs, the

signal sensitivity issue can be avoided.

SPORT0_CLK_I

SPORT0_CLK_O

SPORT0_CLK_PBEN_O

SPORT0_FS_PBEN_O

Figure 10-1. SRU Configuration when SPORT is Master Receiver.

Register Overview

This section provides brief descriptions of the major registers. For com-

plete information,

Serial Port Control Registers (SPCTLx). The

serial port modes and are part of the

registers. Other bits in these registers set up DMA and I/O processor

related serial port features. For information about configuring a specific

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

see"Serial Port Registers" on page

where the clock and

registers control

(transmit and receive) control

Serial Ports

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