Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 619

Table of Contents

• Programmable baud rates, clock polarities, and phases (SPI mode

• Master or slave booting from a master SPI device. See

Booting" on page

• DMA capability to allow transfer of data without core overhead.

"DMA Transfers" on page

• Internal loopback mode (by connecting

Note the SPI interface does not support daisy chain operation, where the

pins are internally connected through a FIFO, allowing

bypass of data streams.

Pin Descriptions

The SPI protocol uses a 4-wire protocol to enable full-duplex serial com-

shows the master-slave connections between two devices.

Table 15-2. SPI Pin Descriptions

Internal Node

SPIB_CLK_I/O

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

Serial Peripheral Interface Ports

provides detailed pin descriptions and

SPI Clock Signal. This control line is clock driven by the master

and regulates the flow of the data bits. The master may transmit

data at a variety of baud rates. The CLK line cycles once for each

bit that is transmitted. It is an output signal if the device is config-

ured as a master; it is an input signal if configured as a slave.

SPI Slave Device Select. This is an active-low input signal that is

used to enable slave devices. This signal is like a chip select signal

for the slave devices and is provided by the master device. For a

master device, it can act as an error input signal in a multi-master

environment. In multi-master mode, if the /SPIDS input signal of

a master is asserted (Low) an error has occurred. This means that

another device is also trying to be the master.

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