Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 648

Programming Model
Slave Mode Transfers
When the SPI is configured as a master, regardless of core or DMA the
SPI ports should be configured and transfers started using the following
steps.
1. Route all required signals (
including the
2. Write to the
device as a slave and configuring the SPI system by specifying the
appropriate word length, transfer format and other necessary infor-
mation. For DMA operation set
The next steps are dependant on whether the access is a core or a DMA
access.
Core Slave Transfers
The following steps illustrate SPI operation in slave mode.
1. Write the data to be transmitted into the
for the data transfer.
2. When a device is enabled as a slave, the start of a transfer is trig-
gered by a transition of the
(low) or by the first active edge of the clock (
the state of
3. The reception or transmission continues until
or until the slave has received the proper number of clock cycles.
4. The slave device continues to receive or transmit with each new
falling-edge transition on
15-32
www.BDTIC.com/ADI
MOSI
as slave select input.
SPI_DS_I
and keep the (
SPICTLx
SPI_DS_I
.
CPHASE
SPI_DS_I
ADSP-214xx SHARC Processor Hardware Reference
, , ) for slave mode
MISO SPICLK
) cleared, enabling the
SPIMS
= 10.
TIMOD
buffer to prepare
TXSPIx
select signal to the active state
SPICLK
SPI_DS_I
or active
SPICLK
), depending on
is released
clock edge.