Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 769

PLL VCO
The VCO is the PLL output stage of the PLL. It feeds the output clock
generator which provides core and peripheral clocks as shown in
Table 22-1. Two settings have an impact on the VCO frequency:
• The
INDIV
• The
PLLM
unit.
Changing the VCO frequency requires a new condition for the PLL cir-
cuitry. Therefore, the core needs to wait a specific settling time in bypass
mode before it can be released for further activities (typically 4096
cycles).
Table 22-1. VCO Encodings
PLLM Bit Settings
0
1
2
N = 3–62
63
1 For operational limits for the VCO clock see the appropriate product data sheet.
Output Clock Generator
The output clock generator post divides the VCO clock to the core ratio
or peripherals ratio and synchronizes all output clocks. It is fed with the
VCO clock and does not provide any feedback back to the PLL circuit.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bit enables the
CLKIN
bits and the
CLK_CFG1–0
INDIV = 0
128x
2x
4x
2Nx
126x
Power Management
input pre-divider by 2.
pins control the PLL multiplier
1
VCO Frequency
INDIV = 1
64x
1x
2x
Nx
63x
CLKIN
22-5