Dma Chaining; Tcb Memory Storage - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Operating Modes

DMA Chaining

DMA data transfers can be set up as continuous or periodic. Furthermore,
these DMA transfers can be configured to run automatically using chained
DMA. With chained DMA, the attributes of a specific DMA are stored in
internal memory and are referred to as a Transfer Control Block or TCB.
The DMA controller loads these attributes in chains for execution. This
allows for multiple chains that are an finite or infinite.

If chaining is enabled on a DMA channel, programs should not use
polling to determine channel status as this gives inaccurate infor-
mation where the DMA appears inactive if it is sampled while the
next TCB is loading.

TCB Memory Storage

The location of the DMA parameters for the next sequence comes from
the chain pointer register that points to the next set of DMA parameters
stored in the processor's internal memory. In chained DMA operations,
the processor automatically initializes and then begins another DMA
transfer when the current DMA transfer is complete. Each new set of
parameters is stored in a user-initialized memory buffer or TCB for a cho-
sen peripheral.

The size of a TCB varies and is based on the peripheral to be used:
the SPORTs, link ports and SPI require four locations, the external
port requires six to 13 locations, the accelerator five to 13 loca-
tions. Allowing different TCB sizes reduces the memory load since
only the required TCBs are allocated in internal memory.
Table 2-27. Principal TCB Allocation for a Serial Peripheral
Address
CPx
CPx + 0x1 (ICx)
2-32
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Table 2-27 provides a brief description of the TCBs.
Register
Chain pointer register
Internal count register
ADSP-214xx SHARC Processor Hardware Reference
Description
Chain pointer for DMA chaining
Length of internal buffer