Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 945

31 30
SRC2_CLK_OP_I (29–25)
Sample Rate Converter 2
Clock Output Input
15
SRC1_CLK_OP_I (19–15)
Sample Rate Converter 1
Clock Output Input
SRC1_CLK_IP_I (14–10)
Sample Rate Converter 1
Clock Input Input
Figure A-53. SRU_CLK1 Register (RW)
31 30
IDP2_CLK_I (29–25)
Input Data Port 2 Clock Input
15
IDP0_CLK_I (19–15)
DIT_CLK_I (14–10)
SPDIF Transmitter Clock Input
SRC3_CLK_OP_I (9–5)
Sample Rate Converter 3 Clock Output Input
Figure A-54. SRU_CLK2 Register (RW)
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Registers Reference
21 20 19 18 17 16
6 5 4 3 2 1 0
21 20 19 18 17 16
IDP0_CLK_I (con't) (19–15)
Input Data Port 0 Clock Input
IDP1_CLK_I (24–20)
Input Data Port 1 Clock Input
6 5 4 3 2 1 0
SRC3_CLK_IP_I (4–0)
Sample Rate Converter 3
Clock Input Input
SRC1_CLK_OP_I (19–15)
Sample Rate Converter 1
Clock Output Input
SRC2_CLK_IP_I (24–20)
Sample Rate Converter 2
Clock Input Input
SRC0_CLK_IP_I (4–0)
Sample Rate Converter 0
Clock Input Input
SRC0_CLK_OP_I (9–5)
Sample Rate Converter 0
Clock Output Input
A-119