Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 988

Peripherals Routed Through the DAI
31 30
DXS_A (31–30)
Data Buffer Channel A Status
DERR_A
Channel A Error status
DXS_B (28–27)
Data Buffer Channel B Status
DERR_B
Channel B Error Status
SPTRAN
SPORT Data Direction
BHD
Buffer Hang Disable
15
IFS
Internal Frane Sync Select
CKRE
Clock Rising Edge Select
OPMODE
SPORT Operation Mode
ICLK
Internal Clock Select
Figure A-88. SPCTLx Register – Packed and Multichannel Mode
A-162
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29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
ADSP-214xx SHARC Processor Hardware Reference
21 20 19 18 17 16
LMFS/L_FIRST
Active Low Multichannel
Frame Sync Select/Channel
Order First
SDEN_A
SPORT DMA Channel
A Enable
SCHEN_A
SPORT DMA Channel A
Chaining Enable
SDEN_B
SPORT DMA Channel B
Enable
SCHEN_B
SPORT DMA Channel B
Chaining Enable
6 5 4 3 2 1 0
DTYPE (2–1)
Data Type
LSBF
Serial Word Bit Order
SLEN (8–4)
Serial Word Length
PACK
16/32 Packing