Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 439

Table 9-4. DAI Routing Capabilities
DAI Group Input (xxxx_I)
F–Pin Buffer DAI Pin Buffer Enable
20–1
G–Shift Register SR_CLK_I
(ADSP-2147x SR_LAT_I
only) SR_SDI_I
DPI Routing Capabilities
Table 9-2 provides an overview about the different routing capabilities for
the DPI unit.
Table 9-5. DPI Routing Capabilities
DPI Group Input (xxxx_I)
A–Miscellaneous SPI (MOSI, MISO, DS, CLK)
Signals SPIB (MOSI, MISO, DS, CLK)
TWI (Clock, Data)
UART0 RX data
Timer1–0
FLAG15–4/PWM3–1
MISCB8–0
DPI Interrupt 13–5
B–Pin Buffer DPI Pin Buffer Input
Input
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Digital Application/Digital Peripheral Interfaces
Output (xxxx_O)
SPORT7–0 (clock, FS, data, TDV)
MISCA5–0
SPORT7-0 (clk, FS)
SPORT7-0 AB (data)
PCG A-B (clk, FS)
DAI Pin Buffer 8-1
SR_CLK, SR_LAT, SR_SDI
Output (xxxx_O)
Timer1–0
UART0 TX Data
Timer1–0
UART0 TX data
SPI (MOSI, MISO, DS, CLK,
SPIFLG)
SPIB (MOSI, MISO, DS, CLK,
SPIBFLG)
FLAG15–4/PWM3–1
PCG (C, D) (clock, FS)
Logic level high
Logic level low
DPI Pin Buffer
Logic level high
Logic level low
9-25