Dma Transfer; Interrupts - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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DMA Transfer

Two DMA channels are used for memory-to-memory DMA transfers. The

write DMA channel has higher priority over the read channel. The trans-

fer is started by a write DMA to fill up the MTM buffer with a 2 x 32-bit

word. Next, the buffer is read back over the same IOD bus to the new des-

tination. With a two position deep buffer and alternate write and read

access over the same bus, throughput is limited. The memory-to-memory

DMA control register (

64-bit data from one internal memory location to another. This register

also allows verification of current DMA status during writes and reads.

There are two DMA channels; one write channel and one read channel.

When the transmission of a complete data block is performed, each chan-

nel will generate an interrupt to signal that the entire block of data has

been processed. Note that the write and read interrupts (

one interrupt is triggered.

provides an overview of MTM interrupts.

Table 5-2. MTM Interrupt Overview

Interrupt Condition

– WR DMA done

(2 channels)

– RD DMA done

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) allows programs to transfer blocks of

Internal transfer

ADSP-214xx SHARC Processor Hardware Reference

RTI instruction

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