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FFT Accelerator
Features
The following list describes the features available through the FFT
accelerator.
• Supports FFT sizes from 16 – 8k
no core intervention.
• Computes a radix 2 decimation in time algorithm with automated
bit reversal.
• Contains a 1024 32-bit word data memory unit.
• Contains a 512 32-bit word twiddle coefficients memory unit.
• Contains a compute block unit with four floating-point multipliers
and six floating-point adders.
• Has a control unit with configuration registers, responsible for all
memory addresses and strobe generation.
• Contains a 8 x 32 deep input/output FIFO unit.
Register Descriptions
The accelerator has two control and two status registers that are used to
program and check operation of the module. The module also contains
DMA registers which are described
Processor.
Power Management Control Register (PMCTL1). Used for FFT acceler-
ator selection. Controls the clock power down to the module if not
required.
Global Control Register (FFTCTL1). Used to enable, start, and reset the
FFT module. It is also used to enable DMA and debug operation.
6-4
www.BDTIC.com/ADI
2
in"I/O Processor" in Chapter 2, I/O
ADSP-214xx SHARC Processor Hardware Reference
points all handled by DMA with
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