Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 838

System and Power Management Registers
Table A-4. PMCTL1 Register Bit Descriptions (RW) (Cont'd)
Bit Name
16 ACCOFF
18–17 ACCSEL
19 MLBOFF
31–20 Reserved
ADSP-2147x/ADSP-2148x Power Management
Registers
The registers described in the following sections are specific to the
ADSP-2147x and ADSP-2148x processors.
Power Management Control Registers (PMCTL)
The following sections describe the registers associated with the processors
power management functions.
The power management control register, shown in
memory-mapped register. This register contains bits to control phase lock
loop (PLL) multiplier and divider (both input and output) values, PLL
bypass mode, and clock enabling control for peripherals (see
This register also contains status bits, which keep track of the status of the
pins (read-only). The reset value of
CLK_CFG
pins (bits 5–0 and 17–16).
CLK_CFG
A-12
www.BDTIC.com/ADI
Description
Shutdown Clock to Accelerator.
0 = Accelerator is in normal mode
1 = Shutdown clock to accelerator
Accelerator Select.
00 = Select FIR
01 = Select IIR
10 = Select FFT
11 = Reserved
Shutdown Clock to Media Local Bus.
0 = MLB is in normal mode
1 = Shutdown clock to MLB
ADSP-214xx SHARC Processor Hardware Reference
Figure A-4, is a 32-bit
Table
is dependent on the
PMCTL
A-5).