Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 863

Table A-17. DDR2RRC Register Bit Descriptions (RW)
Bit
13–0
20–14
28–21
31–29
Controller Status Register 0 (DDR2STAT0)
The register (Figure A-14
state of the controller. This information can be used to determine when it
is safe to alter DDR2 controller control parameters or as a debug aid.
15
DDR2DLLCALDONE
Calibration Complete
DDR2DLLCAL
Calibration Active
DDR2PD
Precharge Power-Down Status
DDR2MSE
Access Error
Figure A-14. DDR2STAT0 Register
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Name Description
RDIV RDIV value defines the number of clock cycles between
two refresh commands.
Reserved
t Row refresh interval minimum refresh interval in clock
RFC
cycles. Programmable from 0 to 255.
Reserved
and Table
14 13 12 11 10 9 8 7
Registers Reference
A-18) provides information on the
6 5 4 3 2 1 0
DDR2CI
Controller Idle Status
DDR2SRA
Self Refresh Active
DDR2PUA
Power Sequence
Active
DDR2RS
Reset State
A-37