Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 407

The lower 14 bits (00 0001 0000 0000) and the 2 reserved bits "00" are
written in the
MLB_CNBCRx
to bits 31–16 in the
for the end address). The remaining higher 5 bits (1 0000) are written in
one of the the base address registers, depending on the transfer mode. For
example, if using synchronous mode, write bits 31–16 = 0x0010 for
receive and bits 15–0 for transmit in the
The base address registers and offset registers use round robin arbitration
to determine which logical channel is granted access to the DMA bus.
more information, see "Programming Model" on page 8-16.
Ping-Pong DMA
Logical channels operate in ping-pong DMA mode when the channel
mode select bits (
figured in ping-pong mode, the
used to configure and monitor the system memory current buffer and next
buffer respectively. Ping-pong DMA is available for all data types.
When receiving and transmitting asynchronous and control packet data,
the current buffer and next buffer are independent internal memory buf-
fers. This allows hardware to support the ping-pong buffering. Each buffer
is addressed using two 16-bit address fields in the
registers as described below.
MLB_CCBCRx
• Next Buffer Start Address – CNBCRx.BSA – beginning of next
buffer in internal memory
• Next Buffer End Address – CNBCRx.BEA – ending of next buffer
in internal memory
• Buffer Current Address – CCBCRx.BCA – beginning of current
buffer in internal memory
• Buffer Final Address – CCBCRx.BFA – ending of current buffer in
internal memory
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register (write 0000 0100 0000 0000 = 0x0400
register for the start address or bits 15–0
MLB_CNBCRx
register bits 25–26) = 00. When MLB is con-
MLB_CECRx
MLB_CCBCRx
Media Local Bus
register.
MLB_SBCR
and
MLB_CNBCRx
MLB_CNBCRx
For
registers are
and
8-11