Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 833

Power Management Control Registers (PMCTL)
The following sections describe the registers associated with the processors
power management functions.
The power management control register, shown in
memory-mapped register. This register contains bits to control phase lock
loop (PLL) multiplier and divider (both input and output) values, PLL
bypass mode, and clock enabling control for peripherals (see
page A-8). This register also contains status bits, which keep track of the
status of the
CLK_CFG
dent on the
CLK_CFG
31 30
LCLKR (22–21)
Link Port Clock Ratio
15
PLLBP
PLL Bypass
DIVEN
PLL Divider Enable
Figure A-2. PMCTL Register
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
pins (read-only). The reset value of
pins (bits 5–0 and 17–16).
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Registers Reference
Figure
21 20 19 18 17 16
CRAT (17–16)
PLL Clock Ratio
DDR2CKR
Core Clock to DDR2 Clock
6 5 4 3 2 1 0
PLLM (5–0)
PLL Multiplier
PLLD (7–6)
PLL Divider
INDIV
Input Divider
A-2, is a 32-bit
Table A-3 on
is depen-
PMCTL
A-7