Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 926

Peripheral Registers
Synchronous Base Address Register (MLB_SBCR)
The , described in
MLB_SBCR
tem memory buffers of all synchronous channels in the device.
Table A-62. MLB_SBCR Register Bit Descriptions (RW)
Bit Name
4–0 STBA
15–5 Reserved
20–16 SRBA
31–21 Reserved
Asynchronous Base Address Register (MLB_ABCR)
The register, described in
MLB_ABCR
the system memory buffers of all asynchronous channels in the device.
Table A-63. MLB_ABCR Register Bit Descriptions (RW)
Bit Name
4–0 ATBA
15–5 Reserved
20–16 ARBA
31–21 Reserved
A-100
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Table A-62, holds the base address of the sys-
Description
Synchronous transmit base address for DMA mode
Synchronous receive base address for DMA mode
Table
Description
Asynchronous transmit base address for DMA mode
Asynchronous receive base address for DMA mode
ADSP-214xx SHARC Processor Hardware Reference
A-63, holds the base address of