Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 977

SPORT Divisor Registers (DIVx)
These registers, shown in
sync divisor and clock divisor.
31 30 29 28 27 26 25 24
15 14 13
CLKDIV
Clock Divisor
Figure A-85. DIVx Register (RW)
Serial Control Registers (SPCTLx)
The registers are transmit and receive control registers for the cor-
SPCTLx
responding serial ports (SPORT 0 through 7). These registers change
depending on operating mode. Figures and bit descriptions are provided
as follows.
• Serial mode –
2
• I S and Left-Justified modes –
Table A-85 on page
• Packed and Multichannel mode –
Table A-86 on page
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Figure A-85, allow programs to set the frame
23 22 21 20 19 18 17 16
12 11 10 9 8 7 6 5
Figure A-86 and
A-159.
A-163.
Registers Reference
FSDIV
Frame Sync Divisor
4 3 2 1 0
Table A-84 on page
Figure A-87 on page A-158
Figure A-88 on page A-162
A-153.
and
and
A-151