Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 792

Processor Booting
Table 23-2. AMICTL1 Boot Settings (0x5C1) (Cont'd)
Bit
5
10–6
13–11
16–14
17
20–18
21
Table 23-3. EPCTL Boot Settings (0xF0)
Bit
0
1
2
3
5–4
7–6
10–8
14–12
18–15
21–19
Table 23-4. DMAC0 Boot Settings (0x1000001)
Bit
0
1
2
23-10
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Name Setting
ACKEN ACK pin disabled (cleared = 0)
WS 23 wait state cycles = 10111
HC Bus hold cycle at the end of write access = 000
IC No bus idle cycle = 000
FLSH Buffer holds data (cleared = 0)
RHC Read hold cycle at the end of read access = 000
PREDIS Disable Predictive Reads (cleared = 0)
Name Setting
B0SD No SDRAM bank 0 (cleared = 0)
B1SD No SDRAM bank 1 (cleared = 0)
B2SD No SDRAM bank 2 (cleared = 0)
B3SD No SDRAM bank 3 (cleared = 0)
EPBR Rotating priority core vs. DMA (11)
DMAPR Rotating priority EPDMA ch0 vs. EPDMA ch1 (11)
FRZDMA No DMA freezing (00)
FRZCR No core freezing (00)
DATE No pack mode (0000) (ADSP-2147x/2148x only)
FRZSP No SPORT DMA freezing (000)
Name Setting
DMAEN DMA enabled (set = 1)
TRAN Write to internal memory (cleared = 0)
CHEN No DMA chaining (cleared = 0)
ADSP-214xx SHARC Processor Hardware Reference