Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 760

Programming Model
3. Program the
interrupts should occur with each byte transmitted (8 bits) or with
each 2 bytes transmitted (16 bits).
4. Program the
desired interrupt sources. For example, programming the value
0x0030 results in an interrupt output to the processor when the
master transfer completes, or if a master transfer error has occurred.
5. Program the
mode operation. As an example, programming the value 0x0201
enables master mode operation, generates a 7-bit address, sets the
direction to master-transmit, uses standard mode timing, and
transmits 8 data bytes before generating a stop condition.
Table 21-6 shows what the interaction between the TWI controller and
the processor might look like using this example.
Table 21-6. Master Mode Transmit Setup Interaction
TWI Controller Master
Interrupt: TWITXINT – Transmit buffer has 1 or
2 bytes empty (according to XMTINTLEN).
...
Interrupt: TWIMCOMP – Master transfer com-
plete.
Master Mode Receive
Follow these programming steps for a single master mode transmit:
1. Program the
ted during the address phase of the transfer.
21-22
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register. Indicate if transmit FIFO buffer
TWIFIFOCTL
register. Enable the bits associated with the
TWIIMASK
register. This prepares and enables master
TWIMCTL
register. This defines the address transmit-
TWIMADDR
ADSP-214xx SHARC Processor Hardware Reference
Processor
Write transmit FIFO buffer.
Change on the next sides always.
Interrupt Acknowledge: W1C the TWI-
IRPTL register.
...
Change on the next sides always.
Interrupt Acknowledge: W1C the TWI-
IRPTL register