Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 767

multiplication range, the processor uses a combination of programmable
multipliers in the PLL feedback circuit and output configuration blocks.
The processor uses an on-chip, phase-locked loop (PLL) to generate its
internal clock, which is a multiple of the
requires some time to achieve phase lock and
minimum time period during reset before the
serted. For information on minimum clock setup, external crystal use, and
range for any given
sheet.

A detailed diagram along with specific equations on the derivation
of VCO frequency with reference to
appropriate product data sheet.
PLL Input Clock
If an external clock oscillator is used, it should NOT drive the
when the processor is not powered. The clock must be driven immediately
after power-up; otherwise, internal gates stay in an undefined (hot) state
and can draw excess current. After power-up, allow sufficient time for the
oscillator to start up, reach full amplitude, and deliver a stable
to the processor before the reset is released. This may take several millisec-
onds and depends on the choice of crystal, operating frequency, loop gain
and capacitor ratios. For details on timing, refer to the appropriate prod-
uct data sheet.
Pre-Divider Input
This unit divides the PLL input clock by 2 if enabled (using the
bit). The pre-divider input is part of the PLL loop, therefore, if a program
changes the PLL input clock (affecting the VCO frequency), the PLL
must be put in bypass mode before the change is made. This is described
in "Bypass Mode" on page
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
frequency, see the appropriate product data
CLKIN
22-7.
Power Management
frequency. The PLL
CLKIN
must be valid for a
CLKIN
signal can be deas-
RESET
can be found in the
CLKIN
pin
CLKIN
signal
CLKIN
INDIV
22-3