Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 213

Force Load Mode Register
Programs can use the Force LMR command by setting bit 22 (=1) in the
register. The Force LMR bit allows changes to the
DDR2CTL0
based settings during runtime. These settings include bit 22 (=1) for MR
command (settings
Force Auto-Refresh
Bit 20 (=1) in the
ately executed (not waiting until the refresh counter has expired). This is
useful for test purposes but also to synchronize the refresh time base with a
system relevant time base.
Force Extended Mode Register 1–3
Programs use the Force extended mode register 1–3 commands (
register) by setting:
bit 23 (=1) for EMR1 command (settings
bit 12 (=1) for EMR2 command (settings
bit 17 (=1) for EMR3 command (settings
This allows programs to initialize or change the content of the
register.
Force DLL External Bank Calibration
The last step during power up is the post calibration of the external
DDR2 banks. This command is enabled by setting bit 13 (=1) in the
register. If enabled the DDR2 controller posts 300 dummy reads
DDR2CTL0
for calibration between the internal DDR2 clock and the
pins which are driven during the read. Note the calibration is done sepa-
rately for each assigned external bank.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register).
DDR2CTL2
register forces the auto refresh to be immedi-
DDR2CTL0
External Port
MODE
register)
DDR2CTL3
register)
DDR2CTL4
register)
DDR2CTL5
DDR2_DQS1-0
register
DDR2CTL0
EMR
3-83