Effect Latency ............................................................................. 9-42
Programming Model ................................................................... 9-42
Features ...................................................................................... 10-2
Pin Descriptions ......................................................................... 10-4
SRU Programming ...................................................................... 10-5
Register Overview ....................................................................... 10-7
Clocking ..................................................................................... 10-8
Master Clock ......................................................................... 10-8
Master Frame Sync ................................................................ 10-9
Slave Mode .......................................................................... 10-10
Architecture ........................................................................ 10-11
Companding the Data Stream ......................................... 10-13
Transmit Path ................................................................. 10-14
Receive Path ................................................................... 10-15
Frame Sync ......................................................................... 10-16
Sampling Edge ................................................................ 10-16
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Contents
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