Dai Miscellaneous Interrupts; Dpi Miscellaneous Interrupts - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

DAI Miscellaneous Interrupts

As described above, the DAI interrupt controller registers provide 10 inde-
pendently-configurable interrupts labeled as
on the routed DAI inputs
event in
DAI_IMASK

There are two signal naming conventions: the DAI interrupt con-
troller bits are named
signals are named
Signals from the SRU can be used to generate interrupts. For example,
when
DAI_30_INT
the external miscellaneous channel A2 generate an interrupt. If set to one,
DAI interrupts trigger an interrupt in the core and the interrupt latch is
set. A read of this bit does not reset it to zero. The bit is only set to zero
when the cause of the interrupt is cleared. A DAI interrupt indicates the
source (in this case, external miscellaneous A, channel 2), and checks the
IVT for an instruction (next operation) to perform.
Table 9-6 provides an overview of DAI miscellaneous interrupts.
Table 9-6. DAI Miscellaneous Interrupt Overview
Interrupt Interrupt Condition
Source
DAI MISCA – Rising edge
(10 channels) – Falling edge
– Rising/falling edge

DPI Miscellaneous Interrupts

As described above, the DPI interrupt controller registers provide 9 inde-
pendently-configurable interrupts labeled as
the routed DPI inputs
if enabled.
DPI_13-5_INT
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Digital Application/Digital Peripheral Interfaces
DAI_INT_31-22_I
register if unmasked.
DAI_31-22_INT
DAI_INT_31-22_I
(bit 30) of
DAI_IMASK_H
Interrupt
Completion
MISCB8-0_I
DAI_31-22_INT
can cause an interrupt latch
and its corresponding SRU
.
is set to one, any signals from
Interrupt
Acknowledge
Read-to-clear
DAI_IRPTL_x
+ RTI instruction
DPI_13-5_INT
can cause an interrupt latch event in
. Any trigger
Default IVT
P0I, P12I
. Any trigger on
9-35