Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 637

transfer occurs when the
been received and latched into the receive buffer,
shortly after the last sampling edge of
latency for a master/slave device, depending on synchronization. This is
independent of the
Backward Compatibility
To maintain software compatibility with other SPI devices (68HC11), the
SPI transfer finished bit (
have slightly different behavior from that of other commercially available
devices. For a slave device,
device, is set one-half (0.5) of the
SPIF
edge, regardless of
bit is set. In general,
SPIF
settings (
SPIBAUD
quently before new data has been latched into the
for = 2 or
SPIBAUD
be set (after
SPIF
settings (
BAUD SPIBAUD
DMA Transfers
The SPI ports support both master and slave mode DMA. DMA is
enabled for
TIMOD

Enable the SPI port before enabling DMA.
For master mode, a DMA transfer starts after the DMA engine is enabled.
For slave mode the slave select pin (
slave DMA operation.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Serial Peripheral Interface Ports
bit is set. This indicates that a new word has
RXS
and
CPHASE TIMOD
) is also available for polling. This bit may
SPIF
is set at the same time as
SPIF
or . The baud rate determines when the
CPHASE CLKPL
is set after
SPIF
< 4). The SPIF bit is set before the
= 3, the processor must wait for the
SPIBAUD
is set) before reading the
> 4), is set before
RXS
bit = 10.
SPI_DS_I
. The
RXSPI
. There is a 4
SPICLK
bit settings and the baud rate.
RXS
period after the last
SPICLK
, but at the lowest baud rate
RXS
RXS
buffer. Therefore,
RXSPI
buffer. For larger
RXSPI
.
SPIF
) needs to be asserted to start
bit is set
RXS
cycle
PCLK
. For a master
SPICLK
bit, and conse-
bit to
RXS
SPI-
15-21