Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 750

Data Transfer
Data Transfer
The TWI uses its transmit and receive buffers for data transfer (no DMA
capability). These buffers are described in the following sections.
Data Buffers
The TWI has two data buffer FIFOs, which are described in the following
sections.
8-Bit Transmit FIFO Register
The TWI 8-bit transmit FIFO register (
holds an 8-bit data value written into the FIFO buffer. Transmit data is
entered into the corresponding transmit buffer in a first-in, first-out order.
Although peripheral bus writes are 32 bits, a write access to the
register adds only one transmit data byte to the FIFO buffer. With each
access, the transmit status (
updated. If an access is performed while the FIFO buffer is full, the core
waits until there is at least one byte space in the transmit FIFO buffer and
then completes the write access.
15 14 13 12 11 10 9 8
Figure 21-7. 8-Bit Transmit FIFO Register
16-Bit Transmit FIFO Register
The TWI 16-bit FIFO transmit register (
holds a 16-bit data value written into the FIFO buffer. Although periph-
eral bus writes are 32 bits, a write access to the
two transmit data bytes to the FIFO buffer. To reduce interrupt output
21-12
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) field in the
TWITXS
7 6 5 4 3 2 1 0
ADSP-214xx SHARC Processor Hardware Reference
) shown in
TXTWI8
TWIFIFOSTAT
XMTDATA8 (7–0)
Transmit FIFO 8-Bit
Data
) shown in
TXTWI16
register adds only
TXTWI16
Figure 21-7
TXTWI8
register is
Figure 21-8