Address Width Settings - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual


For two-banked SDRAMs, connect BA with A17. Note that page
interleaving is not supported with 2 bank devices.
CORE ADDRESS MAPPING, TO ROW, COLUMN ADDRESSES (Page Interleaving, SDADDRMODE=1)
31
Row Address
Unused
CORE ADDRESS MAPPING, TO ROW, COLUMN ADDRESSES (Bank Interleaving, SDADDRMODE=0)
31
Bank
Unused
Address
Figure 3-7. Core Address Mapping—Page and Bank Interleaving

The mapping of the addresses depends on the row address width
( ), column address width (
SDRAW
(
SDADDRMODE

Address Width Settings

Address width settings can be configured as shown in
Table 3-6. External Memory Address Bank Decoding
IA[27]
0
0
1
1
Number of Internal Banks. The controller assumes the SDRAM is com-
prised of four bank devices. However, SDRAM can use two bank devices
by not connecting the
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Bank
Address
Row Address
) setting.
IA[26]
0
1
0
1
pin.
ADDR18
Column Address
Column Address
), and the address mode bit
SDCAW
Table
External Bank
Bank 0
Bank 1
Bank 2
Bank 3
External Port
0
0
3-11.
3-27