Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 753

troller is a slave-receiver. If the data associated with the transfer is to be
not acknowledged (NAKed), the
If the TWI controller is to issue a general call as a master-transmitter, the
appropriate address and transfer direction can be set along with loading
transmit FIFO data.
Fast Mode
Fast mode essentially uses the same mechanics as standard mode. It is the
electrical specifications and timing that are different. When fast mode is
enabled using the
the electrical requirements.
• Serial data rise times before arbitration evaluation (t
• Stop condition setup time from serial clock to serial data (t
• Bus free time between a stop and start condition (t
Interrupts
The following sections provide information on the TWI and interrupt
generation. Table 21-4

If TWI interrupts are routed via the DPI interrupt, programs do
not need to also read the
edge. A write to clear the
DPI_IRPTL
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
TWINAK
bit, the following timings are modified to meet
TWIFAST
provides an overview of TWI interrupts.
DPI_IRPTL
TWIIRPTL
register.
Two Wire Interface Controller
bit can be set.
register for interrupt acknowl-
register also clears the
)
r
)
SUSTO
)
BUF
21-15