Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 874

ADSP-2147x, ADSP-2148x External Port Registers
31 30
PREDIS
Disable Predictive Reads
RHC (20–18)
Read Hold Cycle
15
IC (16–14)
HC (13–11
Bus Hold Cycle
WS (10–6)
Wait States
ACKEN
ACK Pin Enable
Figure A-21. AMICTLx Registers
Table A-26. AMICTLx Register Bit Descriptions (RW)
Bit Name
0 AMIEN
2–1 BW
A-48
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29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Description
AMI Enable. Enables the AMI controller for the dedicated external
bank.
0 = AMI is disabled
1 = AMI is enabled
To access an external memory bank, the AMIEN bit in the corre-
sponding AMICTLx register has to be set. If any of the AMIEN bits
are set, then the AMI is enabled and can access memory. However,
bank selects can not be driven for that bank whose AMIEN is not
set (but read/write strobes can occur).
Any access made to a bank whose AMIEN bit is not set occurs at
WS = 2 and 8-bit mode without any hold/idle cycles. In any case
this access occurs without the bank select and is a void access.
Moreover, the AMIEN bit should not be cleared when an access is
on-going (when the AMIS bit in the AMISTAT register is set).
External Data Bus Width. Select between 8-bit and 16-bit.
00 = 8-bit
01 = 16-bit
10, 11 = Reserved
ADSP-214xx SHARC Processor Hardware Reference
21 20 19 18 17 16
6 5 4 3 2 1 0
AMIEN
AMI Enable
BW
External Data Bus Width
PKDIS
Packing/Unpacking Disable
MSWF
Most Significant Word First
IC
Bus Idle Cycle
AMIFLSH
AMI Buffer Flush