Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 865

Controller Status Register 1 (DDR2STAT1)
This register reports the DDR2 bank active/idle status. This register is
shown in Figure A-15
31 30
Bit Field (31–24)
External Bank 3
Status
15 14
Bit Field (15–8)
External Bank 1
Status
Figure A-15. DDR2STAT1 Register
Table A-19. DDR2STAT1 Register Bit Descriptions (RO)
Bit Field Field Name
7–0 External Bank 0
Status
15–8 External Bank 1
Status
ADSP-214xx SHARC Processor Hardware Reference
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and described in
29 28 27 26 25 24 23 22
13 12 11 10 9 8 7 6
Description
External Bank 0 Active/Precharge State.
xxxxxxx1 = Internal bank 0 in open state
xxxxxxx0 = Internal bank 0 in precharge state
xxxxxx1x = Internal bank 1 in open state
xxxxxx0x = Internal bank 1 in precharge state
...
1xxxxxxx = Internal bank 7 in open state
0xxxxxxx = Internal bank 7 in precharge state
External Bank 0 Active/Precharge State.
xxxxxxx1 = Internal bank 0 in open state
xxxxxxx0 = Internal bank 0 in precharge state
xxxxxx1x = Internal bank 1 in open state
xxxxxx0x = Internal bank 1 in precharge state
...
1xxxxxxx = Internal bank 7 in open state
0xxxxxxx = Internal bank 7 in precharge state
Registers Reference
Table A-19.
21 20 19 18 17 16
Bit Field (23–16)
External Bank 2
Status
5 4 3 2 1 0
Bit Field (7–0)
External Bank 0
Status
A-39