Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 936

Peripheral Registers
Table A-68. MLB_CSCRx Register Description (RO) (Cont'd)
Bit Name
4 STS4
5 STS5
(DMA)
6 STS6
7 Reserved
8 STS8
(I/O)
8 STS8
(DMA)
9 STS9
(I/O)
9 STS9
(DMA)
A-110
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Description
Buffer Error. Indicates that either a TX channel has detected a buffer underflow
(attempt to pop data from an empty buffer), or an RX channel has detected a buf-
fer overflow (attempt to push data onto a full buffer). The setting of this bit gen-
erates a maskable channel interrupt to system software. This bit is valid for
synchronous RX/TX (CECRn.FCE = 0) channels only.
Host Bus Error. Indicates that an HBI bus error has been detected. The setting of
this bit generates a non-maskable channel interrupt to system software.
Lost Frame Sync. Indicates that the logical channel has lost synchronization with
the MediaLB frame. The setting of this bit generates a maskable channel interrupt
to system software. This bit is valid for synchronous channels only.
Receive Packet Abort. Indicates that an RX channel has detected an aborted
packet. Received packets are aborted if the receiver generates a break response,
ReceiverBreak (70h), or detects a transmitter packet break command; Control-
Break (36h) or AsyncBreak (26h). This bit can also indicate the RX channel has
detected a transmit command protocol error. The setting of this bit generates a
maskable channel interrupt to system software. This interrupt can be used by sys-
tem software to detect when it has encountered the beginning of an aborted
packet. This bit is valid for asynchronous and control RX channels only
Previous Buffer Protocol Error. Indicates that either a TX channel has detected
an RxStatus of ReceiverProtocolError (72h), a RX channel has detected an invalid
command for this channel type, or an additional AsyncStart (20h) or Control-
Start (30h) command has been received while in the middle of a packet. The set-
ting of this bit generates a maskable channel interrupt to system software. This bit
is valid for all RX channels and valid for only asynchronous and control TX chan-
nels.
Receive Packet Start. Indicates that an RX channel has detected a transmitter
packet start command; ControlStart (30h) or AsyncStart (20h). This status bit
can be used by system software to detect when it has reached the end of an
aborted packet. This bit is valid for asynchronous and control RX channels only.
Previous Buffer Detect Break. Indicates that either a TX channel has detected a
receiver break response, ReceiverBreak (70h), or an RX channel has detected a
transmitter break command, ControlBreak (36h) or AsyncBreak (26h), while pro-
cessing the Previous Buffer. The setting of this bit generates a maskable channel
interrupt to system software. This bit is valid for all channel types.
ADSP-214xx SHARC Processor Hardware Reference