Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 668

Operating Modes
is generated on the
active low.
Pulse Mode
The waveform produced in PWM_OUT mode with
has a fixed assertion time and a programmable deassertion time (via the
register). When both timers are running synchronously by the same
TMxW
period settings, the pulses are aligned to the asserting edge as shown in
Figure 16-4. Note that the timer does not support toggling of the
bit in each period.
PULSE = 1
PULSE = 1
Figure 16-4. Timers with Pulses Aligned to Asserting Edge
Pulse Width Count and Capture Mode (WDTH_CAP)
To enable WDTH_CAP mode, set the
ter to 10. This configures the
polarity determined by
pulse waveform is measured at the
0), an active low width pulse waveform is measured at the
The internally-clocked timer is used to determine the period and pulse
width of externally-applied rectangular waveforms. The period and width
16-12
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signal. If the
TIMERx_O
TMR0
ACTIVE
HIGH
TMR1
ACTIVE
HIGH
TIMER
ENABLE
signal as an input signal with its
TIMERx
. If
PULSE PULSE
TIMER_Ix
ADSP-214xx SHARC Processor Hardware Reference
bit is not set, the pulse is
PULSE
PRDCNT
PERIOD 1
bits in the
TIMODE1–0
is set (= 1), an active high width
signal. If
PULSE
TIMERx_I
= 1 normally
PULSE
regis-
TMxCTL
is cleared (=
signal.