Pwm Timer Edge Aligned Update - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

PWMPERIOD/2
-PWMPERIOD/2
PWMPHASE BIT
PWM INTERRUPT LATCH
(SINGLE UPDATE MODE)
PWM INTERRUPT LATCH
(DOUBLE UPDATE MODE)
Figure 7-6. Operation of Internal PWM Timer (Center Aligned)

PWM Timer Edge Aligned Update

The internal operation of the PWM generation unit is controlled by the
PWM timer which is clocked at the peripheral clock rate,
ation of the PWM timer over one full PWM period is illustrated in
Figure 7-7. It can be seen that during the first half cycle, the PWM timer
decrements from PWMPERIOD/2 to 0 using a two's-complement count.
At this point, the count direction changes and the timer continues to
increment from 0 to the PWMPERIOD/2 value.
Also shown in Figure 7-7
edge aligned mode. An PWM interrupt is latched at the beginning of
every PWM cycle. Note that the
meaning in this mode and is always set.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
PWM TIME DECREMENTS FROM
PWMPERIOD/2 TO -PWMPERIOD/2
are the PWM interrupt pulses for operation in
PWMPHASE
Pulse Width Modulation
PWM TIME DECREMENTS FROM
-PWMPERIOD/2 TO PWMPERIOD/2
1
PCLK
PCLK
bit ( register) has no
PWMSTAT
. The oper-
7-21