Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 756

Debug Features
or
IMASK LIRPTL
mable interrupt to be used. The ISR needs to clear the status bits of the
register by explicitly writing 1 into the status bit (W1C) as
TWIIRPTL
shown in Listing
Listing 21-3.
TWI_ISR:
ustat1 = dm(TWIIRPTL);
bit set ustat1 TWITXINT;
dm(TWIIRPTL) = ustat1;
instruction;
instruction;
rti;
Debug Features
The following section provides information on debugging features avail-
able with the TWI.
Buffer Hang Disable
To support debugging buffer transfers, the processors have a buffer hang
disable ( ) bit in the
BHD
vents the processor core from detecting a buffer-related stall condition,
permitting debugging of this type of stall condition. For more informa-
tion, see "Buffer Hang Disable (BHD)" on page
Loop Back Routing
The controller supports an internal loop back mode by using the SRU.
For more information, see "Loop Back Routing" on page 9-40.
21-18
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registers must also be configured based on the program-
21-3.
/* W1C to clear TWI TX interrupt */
register. When set (=1), this bit pre-
TWIFIFOCTL
ADSP-214xx SHARC Processor Hardware Reference
10-54.