Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 775

External Port Control
The bit in the
EPOFF
clocks to the SDRAM and AMI modules in order to save power if the con-
trollers are not used. Note that if the SDRAM/DDR2 controller is used
but pauses, the self-refresh mode also helps to reduce power consumption.
For more information, see "SDRAM Controller
(ADSP-2147x/ADSP-2148x)" on page 3-17.
Disabling the SDRAM Controller
If the SDC is not used, the
and reduce power dissipation.

The
DSDCTL
interface to reduce power consumption. Set this bit as early as pos-
sible after booting the part.
Disabling the DDR2 Controller
If the DDR2 interface for ADSP-2146x processor is not used, the follow-
ing bits should be configured in order to provide maximum power
reduction.
• In the
DDR2CTL0
DIS_DDR2CLK1
I/O pads.
• In the
DDR2PADCTL0
register (bits 9 and 19), set (=1) all the
receiver pad).
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register allows programs to disconnect the
PMCTL1
bit can be disabled to stop the clock
DSDCTL
bit must be set (=1) in products without the SDRAM
register, set (=1) the following bits:
and
DIS_DDR2CKE
register (bits 9, 19 and 29) and
Power Management
to disable the controller and its
bits (power-down
PWD
,
DIS_DDR2CTL
DDR2PADCTL1
22-11