Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 868

ADSP-2146x External Port Registers
Table A-21. DLL1CTL1 Register Bit Descriptions (RW)
Bit Name
8–0 Reserved
9 RESETDLL
10 RESETDAT
11 RESETCAL
31–12 Reserved
DLL Status Registers (DLL0STAT0, DLL1STAT0)
The
DLL0STAT0
Table A-22. DLL0STAT0 Register Bit Descriptions (RW)
Bit Name
0–29 Reserved
30 DLL_LOCKED Reset DLL Control Logic. If this bit is set, indicates that the
31 Reserved
A-42
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Description
Reset DLL Control Logic. Active high, when active, it resets the
DLL control logic only, including the 90 degree DQS shifters.
0 = No effect
1 = Reset DLL1 control logic
Reset Data Capture Logic. Active high, when active, it resets the
data capture logic only, including P and N buffers.
0 = No effect
1 = Reset DLL1 reset capture logic
Reset DQS Phase Calibration Logic. Active high, when active, it
resets the DQS phase calibration logic.
0 = No effect
1 = Reset DLL1 DQS phase calibration logic
status register indicates the DLL lock status.
Description
on-chip DLL for DDR2 controller has locked. Note after reset
de-asserted the DLL does automatically lock to the default DDR2
CLK frequency even the DDR2C is not enabled.
ADSP-214xx SHARC Processor Hardware Reference