Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 544

Interrupts
DMA Interrupts
Using DMA transfer overrides the mechanism used for interrupt-driven
core reads from the FIFO. When the
of the
IDP_DMA_ENx
(
IDP_FIFO_GTN_INT
At the end of the DMA transfer for individual channels, interrupts are
generated. These interrupts are generated after the last DMA data from a
particular channel has been transferred to memory. These interrupts
( ) are mapped from the bits 17–10 in the
IDP_DMAx_INT
registers and generate interrupts when they are set (= 1). These bits are
ORed and reflected in high level interrupts that are sent to the DAI
interrupt.
An interrupt is generated at the end of a DMA, which is cleared by read-
ing the
DAI_IMASK_x
FIFO Overflow Interrupts
If the data out of the FIFO (either through DMA or core reads) is not suf-
ficient to transfer at the combined data rate of all the channels, then a
FIFO overflow can occur. When this happens, new data is not accepted.
Additionally, data coming from the serial input channels (except for
2
32-bit I S and left-justified modes) are not accepted in pairs, so that alter-
nate data from a channel is always from left and right channels. If overflow
occurs, an interrupt is generated if the
register is set (sticky bits in
DAI_IMASK_x
Data is accepted again when space has been created in the FIFO.
Note that the total FIFO depth per channel is 9 locations: 1 location for
SIP to parallel data conversion + 8 locations for the
11-24
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IDP_DMA_EN
register are set, the eighth interrupt
IDP_CTL1
) in the
DAI_IMASK_x
registers.
ADSP-214xx SHARC Processor Hardware Reference
bit and at least one
registers is NOT generated.
DAI_IMASK_x
IDP_FIFO_OVR_INT
register are also set).
DAI_STAT0
IDP_FIFO
bit in the
.