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Operating Modes
SPI Modes
The SPI supports four different combinations of serial clock phases and
polarity called SPI modes. The application code can select any of these
combinations using the
Figure 15-5 on page 15-15
Figure 15-6 on page 15-16
Each diagram shows two waveforms for
the other for
CLKPL
slave timing diagrams since the
connected between the master and the slave. The
from the slave (slave transmission), and the
the master (master transmission).
The
signal is generated by the master, and the
SPICLK
sents the slave device select input to the processor from the SPI master.
The diagrams represent 8-bit transfers (
Any combination of the
For example, a 16-bit transfer with the LSB first is one possible
configuration.
The clock polarity and the clock phase should be identical for the master
device and slave devices involved in the communication link. The transfer
format from the master may be changed between transfers to adjust to var-
ious requirements of a slave device.
When
CPHASE
(
) between each word in the transfer. Even in SPI slave mode
HIGH
when
CPHASE
between each transfer. When
active (
LOW
Figure 15-5
shows the SPI transfer protocol for
starts toggling in the middle of the data transfer where the bit set-
SPICLK
tings are
= 0, and
WL
15-14
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and
CLKPL
CPHASE
shows the transfer format when
shows the transfer format when
= 1. The diagrams may be interpreted as master or
SPICLK
and
WL
MSBF
= 0, the slave-select line,
= 0, the master should de assert the
) between successive transfers or be inactive (
= 1.
MSBF
ADSP-214xx SHARC Processor Hardware Reference
bits (10 and 11).
—one for
SPICLK
,
, and
pins are directly
MISO
MOSI
signal is the output
MISO
signal is the output from
MOSI
SPIDS
= 0) with MSB first (
WL
bits of the
register is allowed.
SPICTL
, must be inactive
SPIDS
= 1,
may either remain
CPHASE
SPIDS
= 0. Note that
CPHASE
= 0 and
CPHASE
= 1.
CPHASE
= 0 and
CLKPL
signal repre-
= 1).
MSBF
line
SPIDS
).
HIGH
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