Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 508

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Internal Transfer Completion

Each serial port has an interrupt associated with it. For each SPORT, both

the A and B channel transmit and receive data buffers share the same

interrupt vector. The interrupts can be used to indicate the completion of

the transfer of a block of serial data when the serial ports are configured

for DMA. They can also be used to perform single word transfers (refer to

"Single Word Transfers" on page

interrupts is shown in

Multiple interrupts can occur if both SPORTs transmit or receive data in

the same cycle. Any interrupt can be masked in the

interrupt is later enabled in the

rupt latch bit in the

interrupt has occurred in the same time period.

SPORT interrupts occur on the second peripheral clock (

after the last bit of the serial word is latched in or driven out.

When serial port data packing is enabled (

ters), the transmit and receive interrupts are generated for 32-bit packed

words, not for each 16-bit word.

Each DMA channel has a count register (

initialized with a word count that specifies the number of words to trans-

fer. The count register decrements after each DMA transfer on the

channel. When the word count reaches zero, the SPORT generates an

interrupt, then automatically stops the DMA channel.

Shared Channels

Both the A and B channels share a common interrupt vector in the inter-

rupt-driven data transfer mode, regardless of whether they are configured

as a transmitter or receiver.

www.BDTIC.com/ADI

10-43). The priority of the serial port

Table 2-28 on page

registers must be cleared in case the

ADSP-214xx SHARC Processor Hardware Reference

), which must be

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