Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 886

External Port DMA Control Registers (DMACx)
External Port DMA Control Registers
(DMACx)
The registers control the DMA function of their respective DMA
DMAC0–1
channels. These registers apply to all processors described in this manual
and are shown in
31 30
DIRS
DMA Transfer Direction Status
EXTS
DMA External Interface
Status
WBS
Delay Line Write Back Status
15
INTIRT
Internal DMA Completion interrupt (Control)
TLEN
Tap List DMA Enable
OFCEN
On the Fly Control Loading Enable
WRBEN
Enable Write Back of EPEI After Reads/Writes
DFLSH
Flush DMA FIFO
Figure A-27. DMACx Registers
A-60
www.BDTIC.com/ADI
Figure A-27 and described in
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
ADSP-214xx SHARC Processor Hardware Reference
Table A-32.
21 20 19 18 17 16
DFS (17–16)
DMA FIFO Status
DMAS
DMA Transfer Status
CHS
DMA Chaining Status
TLS
Tap List Loading Status
6 5 4 3 2 1 0
DEN
DMA Enable
TRAN
DMA Direction
CHEN
Chaining Enable
DLEN
Delay Line DMA Enable
CBEN
Circular Buffering Enable