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DDR2 DRAM Controller (ADSP-2146x)
bits in the
DDR2CTL0
shown in
Table
Table 3-11. External Memory Address Bank Decoding
IA[27]
0
0
1
1
Row Address Width (DDR2RAW). These bits in the
determine the row width of the DDR. The
grammed for row widths of 8 to 15.
Column Address Width (DDR2CAW). The DDR2 memory control reg-
ister also includes external bank specific programmable parameters. The
external bank can be configured for a different DDR2 size. The DDR
controller determines the internal DDR2 page size from the
parameters. Page sizes of 256, 512, 1K, 2K and 4K words are
DDR2CAW
supported.
The mapping of the addresses depends on the row address width
(
DDR2RAW
bit (
DDR2ADDRMODE
16-Bit Address Mapping
Even if the external data width is 16 bits, the processor supports only
32-bit data accesses. The DDR2 controller performs two 16-bit accesses to
get and place 32-bit data. The controller takes the IA address and appends
one extra bit to the LSB to generate the address externally.
3-62
www.BDTIC.com/ADI
register. The bank address width is three bits as
3-11.
IA[26]
0
1
0
1
), column address width (
) setting.
ADSP-214xx SHARC Processor Hardware Reference
External Bank
Bank 0
Bank 1
Bank 2
Bank 3
DDRCTL0
bits can be pro-
DDR2RAW
), and the address mode
DDR2CAW
register
and
X16DE
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