Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 542

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Data Transfer

ping-pong DMA, initialize the corresponding

DMA transfers for all 8 channels can be interrupted by changing the

(except for the

bit (= 0) does not affect the data in the FIFO, it only stops DMA transfers.

If the IDP remains enabled, an interrupted DMA can be resumed by

data in the FIFO. If the bit is set again, the FIFO starts accepting new

Programs can drop DMA requests from the FIFO if needed. If one chan-

nel has finished its DMA, and the global

any data corresponding to that channel is ignored by the DMA machine.

This feature is provided to avoid stalling the DMA of other channels,

which are still in an active DMA state. To avoid data loss in the finished

channel, programs can clear (=0)

Multichannel FIFO Status

The state of all eight DMA channels is reflected in the

(bits 24–17 of

channel is transferred. Even if

IDP_DMAx_STAT

fers takes place.

Note that when a DMA channel is not used (that is, parameter reg-

isters are at their default values), the DMA channel's corresponding

IDP_DMAx_STAT

If the combined data rate from the channels is more than the DMA can

service, a FIFO overflow occurs. This condition is reflected for each chan-

nel by the individual overflow bits (

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bit) should be changed. Clearing the

bit again. But resetting the

bits are set, and remain set until the last data from that

bits clear once the required number of data trans-

bit is cleared (= 0).

ADSP-214xx SHARC Processor Hardware Reference

bit is still set (=1),

bit as discussed in

IDP_DMAx_STAT

bit flushes the

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