Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 747

S 7-BIT ADDRESS
S = START
P = STOP
ACK = ACKNOWLEDGE
Figure 21-3. Standard Data Transfer
To better understand the mapping of TWI controller register contents to
a basic transfer,
corresponding TWI controller bit names. In this illustration, the TWI
controller successfully transmits one byte of data. The slave has acknowl-
edged both address and data.
S
S = START
P = STOP
ACK = ACKNOWLEDGE
Figure 21-4. Data Transfer With Bit Illustration
Bus Arbitration
The TWI controller initiates a master mode transmission (
when the bus is idle. If the bus is idle and two masters initiate a transfer,
arbitration for the bus begins. This is illustrated in
The TWI controller monitors the serial data bus (
is high. If
TWI_CLOCK
while the internal TWI controller's data is a logic 1 level, the TWI con-
troller has lost arbitration and ends generation of clock and data. Note
that arbitration is performed not only at serial clock edges, but also during
the entire time
ADSP-214xx SHARC Processor Hardware Reference
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R/W ACK
Figure 21-4 details the same transfer as above noting the
MADDR[6:0] MDIR ACK
is determined to be an active logic 0 level
TWI_DATA
is high.
TWI_CLOCK
Two Wire Interface Controller
8-BIT DATA ACK P
XMITDATA8[7:0] ACK P
Figure
TWI_DATA
) only
TWIMEN
21-5.
) while the
21-9