Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 919

IIR Debug Registers (IIRDEBUGCTL, IIRDEBUGADDR)
The
IIRDEBUGCTL
Table A-56, controls the debug mode operation of the IIR accelerator.
Note that these registers should only be used in debug mode.
31 30
15
IIR_ADRINC
Address Auto Increment
IIR_DBGMEM
Local Memory Access
Figure A-44. IIRDEBUGCTL Register
Table A-56. IIRDEBUGCTL Register Bit Descriptions (RW)
Bits Name
0 IIR_DBGMODE
1 IIR_HLD
2 IIR_RUN
3 Reserved
4 IIR_DBGMEM
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register, shown in
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Description
Debug Mode Enable.
0 = Disable
1 = Enable
For local memory access, the IIRCTL1 register can be
cleared.
Hold or Single Step. The function of this bit is based on the
IIR_DBGMEM bit setting.
For IIR_DBGMEM = 0:
1 = Single step
For IIR_DBGMEM = 1:
1 = Hold data
Release the MAC. This bit is self clearing after one IIR clock
cycle.
Local Memory Access. If set, the data and coefficients mem-
ory can be indirectly accessed.
Registers Reference
Figure A-44 and described in
21 20 19 18 17 16
6 5 4 3 2 1 0
IIR_DBGMODE
Debug Mode Enable
IIR_HLD
Hold or Single Step
IIR_RUN
Release MAC
A-93