Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 98

TCB Storage
For delay line DMA, TCB loading is split into two sequences to improve
overall priority. The first TCB loads the write parameters (
the second loads the read parameters (
is transparent to the application. The order the descriptors are fetched
with circular buffering enabled is shown in
Table 2-24. External Port TCBs for Delay Line DMA
Address
Delay Line Read
CP[18:0]
CP[18:0] + 0x1
CP[18:0] + 0x2
CP[18:0] + 0x3
CP[18:0] + 0x4
CP[18:0] + 0x5
Delay Line Write
CP[18:0] + 0x6
CP[18:0] + 0x7
CP[18:0] + 0x8
CP[18:0] + 0x9
CP[18:0] + 0xA
CP[18:0] + 0xB
CP[18:0] + 0xC
2-20
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RIEP
Register
CPEP
TPEP
TCEP
RMEP
RCEP
RIEP
ELEP
EBEP
EMEP
EIEP
ICEP
IMEP
IIEP
ADSP-214xx SHARC Processor Hardware Reference
IIEP
– ). This two stage loading
CPEP
Table 2-24.
– ) and
ELEP