Ami Initialization - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

3. For a chained DMA, new TCB loading can be inhibited by clearing
the
CHEN
TCB is loaded once
was happening when
4. Before initializing a chained DMA (including delay line) make sure
that the
5. The DMA parameter registers (except
to while chaining is occurring (the
can be read during chaining.
6. A zero count for the
chain pointer with such a descriptor is programmed then the DMA
might hang. So a read count zero or a write count zero for a delay
line DMA is also forbidden.

AMI Initialization

After reset, the
the AMI must be configured and initialized. In order to set up the AMI,
use the following procedure. Note that the registers must be programmed
in order.
1. Chose a valid
2. Assign external banks to the AMI using the
3. Wait at least 8
4. Enable the global
(
AMICTLx
speed and asynchronous memory specifications.
SDCLK
The and
AMIMS
checked to determine the current state of the AMI.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bit while keeping all other control bits the same. The new
bit is re-enabled. The TCB load which
CHEN
was cleared will complete.
CHEN
and registers are zero.
ICEP ECEP
,
ICEP RCEP
is running with the default PLL settings. However,
SDCLK
to
CCLK SDCLK
cycles (effect latency).
PCLK
bit and program the AMI control
AMIEN
) registers. (Define control settings for AMI based on
bits 1–0 of the AMI status register (
AMIS
) should not be written
DMACx
bit is set), but any register
CHS
and registers is forbidden. If a
TCEP
clock ratio in the
PMCTL
EPCTL
External Port
register.
register (default).
) can be
AMISTAT
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