Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 493

three-stated when the time slot is not active, the
ifies if the SPORT data is being driven by the processor.
Unlike previous SHARC processors, the assertion of the
independent for the transmit buffer status (valid data or not). So writing
to the buffer does not affect the
Timing Control Bits
Several bits in the
mode.
• Frame Delay (
• Number of multichannel channels (
• Internal Clock (
• Internal Frame Sync (
• Sampling Edges Frame Sync/Data (
• Logic Level Frame Sync (
• Word Length (
• Word Order (
• Word Packing (
Number of Channels (NCH)
Select the number of channels used in multichannel operation by using
the 7-bit field in the multichannel control register. Set
NCH
actual number of channels minus one (
The 7-bit
CHNL
channel that is currently selected during multichannel operation. This
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
SPORTx_TDV_0
register enable and configure multichannel
SPCTLx
)
MFD
)
ICLK
)
IMFS
LMFS
, 8–32 bits)
SLEN
)
LSBF
)
PACK
field in the multichannel control registers indicates the
SPORTx_TDV_0
output timing.
)
NCH
)
CKRE
)
= Number of channels – 1).
NCH
Serial Ports
signal spec-
is
SPORTx_TDV_0
to the
NCH
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