Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 632

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Operating Modes

CLOCK CYCLE#

(SPI MODE 1)

(SPI MODE 3)

Figure 15-6. SPI Transfer Protocol for CPHASE = 1

asserted (active-low) between transfers or be deasserted between transfers.

This is controlled in software using the

example, to configure

= 1. As soon as this

(slave-select output pin) becomes active (Low).

remains active between transfers.

asserted only for the duration of the transfer. This is controlled by the

internal SPI hardware. In this case, the

example, to configure

Note that the

SPI module is enabled as a master. Otherwise, none of the bits in the

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as a slave-select, set

can be cycled high and low between transfers by

bit to 1 and back to 0. Otherwise,

as a slave-select, it is only necessary to

signals behave as slave-select outputs only if the

ADSP-214xx SHARC Processor Hardware Reference

= 1, all selected outputs are

bits are ignored. For

* = UNDEFINED

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