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Note that each input channel has its own clock and frame sync input, so
unused IDP channels do not produce data and therefore have no impact
on FIFO throughput. The clock and frame sync of any unused input
should be routed by the SRU to low to avoid unintentional acquisition.
The framing format is selected by using the
channel) in the
trol the input format modes for each of the eight channels. The eight
groups of three bits indicate the mode of the serial input for each of the
eight IDP channels.
Figure 11-8
and
the SIP (depending on
RIGHT-JUSTIFIED FORMAT, 24-BIT DATA WIDTH
24 BITS AUDIO DATA
RIGHT-JUSTIFIED FORMAT, 20-BIT DATA WIDTH
20 BITS AUDIO DATA
RIGHT-JUSTIFIED FORMAT, 18-BIT DATA WIDTH
18 BITS AUDIO DATA
RIGHT-JUSTIFIED FORMAT, 16-BIT DATA WIDTH
16 BITS AUDIO DATA
Figure 11-7. IDP Data Buffer Format SIP – Right-Justified
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register. Bits 31–8 of the
IDP_CTL0
Figure 11-7
shows the IDP data buffer input format for
bits) for core access.
SMODEx
Input Data Port
bits (three bits per
IDP_SMODEx
IDP_CTL0
4 BITS,
3 BITS
L/R
SET TO
IDP
BIT
ZERO
CHANNEL
8 BITS,
3 BITS
L/R
SET TO
IDP
BIT
ZERO
CHANNEL
10 BITS,
3 BITS
L/R
SET TO
IDP
BIT
ZERO
CHANNEL
3 BITS
12 BITS,
L/R
SET TO
IDP
BIT
CHANNEL
ZERO
register con-
11-17
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