Can Controller Programming Model; Software Initialization - Altera Cyclone V Device Handbook

cv_54025
2013.12.30
Status Interrupts
The following status conditions generate interrupts:
• Receive OK when the CAN controller receives a message successfully, the RxOK bit in the CAN status
register (CSTS) in the protocol group (protogrp) is set to 1.
• Transmit OK when the CAN controller transmits a message successfully, the TxOK bit in the CAN
status register (CSTS) in the protocol group (protogrp) is set to 1.
• Last error code when a message is received or transmitted with an error, the LEC bits in the CAN status
register (CSTS) in the protocol group (protogrp) are set according to the error type.
Message Object Interrupts
The IntPnd bits from the message objects can generate interrupts when the corresponding message object
TxIE bit or RxIE bit is set to 1. The table lists the location of message object interrupt information in the
interrupt pending registers. The interrupt pending registers are located in the message handler group
(msghandgrp).
Table 25-3: Message Object Interrupt Registers
Register
MOIPA
MOIPB
MOIPC
MOIPD
The MOIPX register allows software to quickly detect which message object group has a pending interrupt.

CAN Controller Programming Model

Software Initialization

The software initialization is started by setting the Init bit in the CAN control register (CCTRL) to 1. While
the Init bit is 1, messages are not transferred to or from the CAN bus, and the CAN_TXD CAN bus output
is held in the high state. Setting the Init bit does not change any configuration registers.
To initialize the CAN controller, the host processor must program the CAN bit timing (CBT) register and
message objects that will be used for CAN communication. If a message object is not needed, it is sufficient
to set the MsgVal bit of the message object to not valid (0), which is the default after RAM initialization.
You must set up the entire message object before setting MsgVal bit to valid (1). The message objects are
set up through either message interface register set.
Access to the CAN bit timing (CBT) register is only enabled when the configuration change enable (CCE)
and Init bits in the CAN control register (CCTRL) are both set to 1.
CAN Controller Introduction
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Title
Interrupt pending A register
Interrupt pending B register
Interrupt pending C register
Interrupt pending D register
Status Interrupts
Message Objects
1 to 32
33 to 64
65 to 96
97 to 128
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