Interrupt Requests - Analog Devices AD9739 Manual

The differential voltage existing between IOUTP and IOUTN
can also be converted to a single-ended voltage via a transformer or
differential amplifier configuration. Internal to the AD9739 is a
differential resistance between IOUTP and IOUTN that must
be factored into the calculations for the voltage output and
impedance out of the DAC. The approximate impedance between
the outputs is 70 Ω.
Depending on the mode of operation and desired signal, the
output stage can be configured in several ways for optimal ac
performance. Figure 107 shows the optimal output network
when measuring the signal in normal mode (baseband).
Figure 108 shows the optimal output network when measuring
the signal in mix mode (second or third Nyquist zone). The
bandwidth of the ADT2T-1T-1P center tap transformer is not
sufficient to support mix mode outputs; therefore, the best
solution is to use the balun by itself.
Finally, when measuring DOCSIS performance, it is necessary
to use a filter between the DAC and the transformer to control
the impedance and help to decrease the folded back harmonics
for higher frequency outputs. The optimal transformer for
DOCSIS measurements is the JTX-2-10T, which is a balun and
center-tapped transformer in one package. This output stage is
shown in Figure 109.
IOUTP
90Ω
70Ω
IOUTN
90Ω
Figure 107. Recommended Transformer Output Stage for Normal Mode
IOUTP
90Ω
70Ω
IOUTN
90Ω
Figure 108. Recommended Transformer Output Stage for Mix Mode
IOUTP
4.7pF
90Ω
70Ω
IOUTN
4.7pF
90Ω
Figure 109. Recommended Transformer Output Stage for DOCSIS
Measurements
MABACT0039
ADT2T-1T-1P
MABACT0039
5.6nH J1
JTX-2-10T
2.2pF
5.6nH

INTERRUPT REQUESTS

There following six interrupt requests (IRQ) can be used for
additional verification of the status of each controller.:
•
Receiver locked
•
Receiver lost lock
•
Mu controller locked
•
Mu controller lost lock
•
Sync controller locked
•
Sync controller lost lock
Each IRQ is enabled using the enable bits in the interrupt mask
register (IMR), Register 0x03 (IRQ_En). The status of the IRQ
can be measured in one of the following ways: via the SPI bits
found in the interrupt service request register (IST), Register
0x04 (IRQ_Req) or using the IRQ pin (Pin F13).
If the pin is used to determine that an interrupt has occurred, it
is also necessary to check Register 0x04 to determine which bit
caused the interrupt because the pin can only indicate that an
interrupt has occurred. To clear an IRQ, it is necessary to write
a 1 to the bit in Register 0x04 that caused the interrupt. A detailed
diagram of the interrupt circuitry is shown in Figure 110.
SPI
DATA
SCLK
IMR
Rev. A | Page 49 of 56
D
INT(n)
Q
INT
SPI WRITE
SOURCE
DATA = 1
Figure 110. Interrupt Request Circuitry
AD9739
(PIN F13)
INT
SOURCE
SPI ISR
READ DATA
SPI ADDRESS