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Programming Model
Programming Model
The programming model for the system interrupts is described in the fol-
lowing sections.
System Interrupt Initialization
If the default assignments shown in
able, then interrupt initialization involves only:
• Initialization of the core Event Vector Table (EVT) vector address
entries
• Initialization of the
• Unmasking the specific peripheral interrupts in
system requires
System Interrupt Processing Summary
Referring to
Figure 4-3 on page
A) is generated by an interrupt-enabled peripheral:
1.
SIC_ISR
are asserted but not yet serviced (that is, an interrupt service rou-
tine hasn't yet cleared the interrupt).
2.
SIC_IWR
state based on this interrupt request.
3.
SIC_IMASK
system level. If interrupt A is not masked, the request proceeds to
Step 4.
4-14
register
IMASK
4-16, note when an interrupt (interrupt
logs the request and keeps track of system interrupts that
checks to see if it should wake up the core from an idled
masks off or enables interrupts from peripherals at the
ADSP-BF537 Blackfin Processor Hardware Reference
Table 4-2 on page 4-11
are accept-
that the
SIC_IMASK
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